[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Jinsong Ji via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 13 07:11:53 PST 2019
jsji added a comment.
@ZhangKang Can we get some performance data for this change. Thanks.
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Comment at: llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll:1389
+; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload
+; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr
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This is way to far from `ld 0,16(1)` now.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D71390/new/
https://reviews.llvm.org/D71390
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