[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang added a comment.

In D71390#1780987 <https://reviews.llvm.org/D71390#1780987>, @lkail wrote:

> Seems currently we haven't modeled `mtlr` correctly. In `PPCFrameLowering`
>
>   if (MustSaveLR)
>     BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);
>   
>
> We might lack a `implicit-def` of `$lr` here. As a result, we might get wrong code if set `hasSideEffect = 0` for `mtlr`. What do you think?


I have do the test, if we use `Uses = [LR8]` like `MFLR`, we will get `M$x0 = MFLR8 implicit $lr8`. And if we use `Defs = [LR8]` like `MTLR`, we will get `MTLR8 $x0, implicit-def $lr8`. So the code you pointed out is right.
In fact, those instructions which use `Uses=[ ]` or `Defs = [ ]` in td files will be added implicit register automatically in MIR.

In D71390#1783562 <https://reviews.llvm.org/D71390#1783562>, @jsji wrote:

> @ZhangKang Can we get some performance data for this change. Thanks.


@jsji , Ok, I will do it soon.


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