[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[qshanz via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/CSR-fit.ll:32
 ; CHECK-PWR8-NEXT:    ld r14, -144(r1) # 8-byte Folded Reload
+; CHECK-PWR8-NEXT:    mtlr r0
 ; CHECK-PWR8-NEXT:    blr
----------------
jsji wrote:
> I see this is actually causing degradation here.  `mtlr` is 5 cycle instruction, moving them together is not a good idea.
> 
It is trying to move it away from the dependency of "ld r0, 16(r1)" which is 4 cycle. The critical path of the region is 9 cycles(4 cycles(ld) + 5 cycles(mtlr)), and the two loads here won't matter too much. So, the scheduling works fine from my view.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71390/new/

https://reviews.llvm.org/D71390