[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D68685#1714539 <https://reviews.llvm.org/D68685#1714539>, @jrtc27 wrote:

> Do we need separate schedule information for compressed and uncompressed instructions? I would assume that any sensible RVC implementation would decode the two to exactly the same control logic (other than for PC incrementing and the original instruction for `mtval`).


We merged the schedule information for c-ext instructions. Thanks.


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