[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:1
+//==- RISCVSchedRocket.td - Rocket Scheduling Definitions -*- tablegen -*-=//
+//
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javed.absar wrote:
> lenary wrote:
> > This should match the filename.
> What are the main differences in terms of schedule between Rocket63 and . Looks like to me that a lot of code can be factored out into a common td
We also think that it should be factored out for the common part. However, we need to provide SchedMachineModel attribute to WriteRes and ReadAdvance and the model is different for Rocket32 and Rocket64. We have no idea how to factor out the common parts. Do you have any suggestions?


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https://reviews.llvm.org/D68685