[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

Wed Nov 27 22:48:32 PST 2019

HsiangKai added a comment.

In D68685#1710474 <https://reviews.llvm.org/D68685#1710474>, @javed.absar wrote:

> Hi Michael:
>
> By the way, thanks for the link - https://www.lowrisc.org/docs/tagged-memory-v0.1/rocket-core/ . But the waybacklink doesnt work for me. Is there an alternate way to get the arch doc. Thanks

Hi @javed.absar,

Thanks for your review and comments. You could find the pipeline model in http://www-inst.eecs.berkeley.edu/~cs250/fa13/handouts/lab2-riscv.pdf, page 13. In addition, SiFive U54 is based on Rocket microarchitecture, so you could also refer to https://sifive.cdn.prismic.io/sifive%2Fac48c4fd-af85-46be-9dd9-22aa34ba6977_u54mc-core-complex-manual-v19.05.pdf for pipeline information. I know the information is limited in the documents. If there is any question that you can not find answer from documents, welcome to raise your questions. Thanks.

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