[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked 3 inline comments as done.
dancgr added a comment.

Also the change on unrelated patterns it to avoid ambiguities in the FPR8 and FPR16 patterns.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:166
   if (Subtarget->hasSVE()) {
+    //addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
+    //addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
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I will be removing both those comment lines.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:237
 
+
 };
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I will be removing this unnecessary extra line.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:6953
 
+
 class SIMDMovAlias<string asm, string size, Instruction inst,
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I will be removing this unnecessary extra line.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69956/new/

https://reviews.llvm.org/D69956