[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Patch uploaded without context.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:169
+    addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass);
+    addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
+
----------------
Is this change necessary?  Making these legal has other effects I don't really want to think about.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69956/new/

https://reviews.llvm.org/D69956