[PATCH] D69956: [AArch64][SVE] Integer reduction instructions pattern/intrinsics.

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr added a comment.

I have added the FPR8 and FPR16 outputs for the SVE Integer reductions.

I have implemented a solution similar to what Sander proposed, but instead I opted for adding v1i8 and v1i16 to the FPR registers in order to simplify the patterns required.

They are handled in the lowering process to get the same result.

I have chosen not to add i8 and i16 types to FPR registers because that would lead to a major refactoring of multiple files.


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https://reviews.llvm.org/D69956