[PATCH] D69601: [Power9] Implement the vector extend sign instruction pattern match
qshanz via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 21 19:57:19 PST 2019
steven.zhang marked an inline comment as done.
steven.zhang added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:933
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
}
----------------
shchenz wrote:
> Do we need these lines? The default action is Legal. If this is necessary, then maybe we need another NFC patch to add operation action for ISD::SIGN_EXTEND_INREG for type {i8, i16, i32} to make actions for ISD::SIGN_EXTEND_INREG be consistent? Up to you to change it or not.
Explicit specify it to legal didn't hurt anything, I think. And we have another patch to specify the default action for SIGN_EXTEND_INREG as Expand for vector type.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D69601/new/
https://reviews.llvm.org/D69601
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