[PATCH] D69601: [Power9] Implement the vector extend sign instruction pattern match
ChenZheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 20 22:55:21 PST 2019
shchenz accepted this revision.
shchenz added a comment.
This revision is now accepted and ready to land.
Thanks for this exploitation. LGTM too.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:933
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
}
----------------
Do we need these lines? The default action is Legal. If this is necessary, then maybe we need another NFC patch to add operation action for ISD::SIGN_EXTEND_INREG for type {i8, i16, i32} to make actions for ISD::SIGN_EXTEND_INREG be consistent? Up to you to change it or not.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D69601/new/
https://reviews.llvm.org/D69601
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