[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Victor Campos via Phabricator via llvm-commits]

vhscampos marked an inline comment as done.
vhscampos added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:9228
   case ISD::STORE:
-    return LowerPredicateStore(Op, DAG);
+    return LowerSTORE(Op, DAG, Subtarget);
   case ISD::MLOAD:
----------------
dmgreen wrote:
> How come this is altered, but not the LowerPredicateLoad?
The custom lowering of loads and stores here is triggered by the DAG Type Legalizer, since i64 is not supported.

In DAGTypeLegalizer::CustomLowerNode(), custom lowering of loads is directed to ARMTargetLowering::ReplaceNodeResults(), which then calls LowerLOAD(), created in the present patch. The lowering of stores is the one that is directed to ARMTargetLowering::LowerOperation().

In summary, the custom lowering of loads because of illegal result types does not go through here, so I believe there's no need to have it changed in this point.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072