[PATCH] D70072: [ARM] Improve codegen of volatile load/store of i64

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:9035
+        ST->getMemOperand());
+  } else if ((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 ||
+              MemVT == MVT::v16i1) &&
----------------
Likewise, this can just say if (Subtarget->hasMVEIntegerOps() && (VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1))

The other cases (isTruncatingStore and isUnindexed) should not come up. If they do we should noisily fail with an assert.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:9228
   case ISD::STORE:
-    return LowerPredicateStore(Op, DAG);
+    return LowerSTORE(Op, DAG, Subtarget);
   case ISD::MLOAD:
----------------
How come this is altered, but not the LowerPredicateLoad?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70072/new/

https://reviews.llvm.org/D70072