[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

steven.zhang marked 2 inline comments as done.
steven.zhang added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:183
   setOperationAction(ISD::VSELECT,           VT, Expand);
-  setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
   if (VT.isInteger()) {
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dmgreen wrote:
> You can leave this line in. It's not bad to be explicit about this being expand.
make sense


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Comment at: llvm/test/CodeGen/Thumb2/mve-sext.ll:4
 
+define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32(<4 x i32> %m) {
+; CHECK-LABEL: sext_v4i32_v4i32:
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dmgreen wrote:
> Can you add equivalents for v8i16, v16i8 and maybe v2i64?
> 
> Or actually, I can do it later. I don't want to give you more work to do.
I will add it.


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https://reviews.llvm.org/D70000