[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 229432.
steven.zhang added a comment.

Address dmgreen's comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000

Files:
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
  llvm/test/CodeGen/ARM/signext-inreg.ll
  llvm/test/CodeGen/Hexagon/signext-inreg.ll
  llvm/test/CodeGen/Thumb2/mve-sext.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70000.229432.patch
Type: text/x-patch
Size: 19214 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191115/08bd45a4/attachment-0001.bin>