[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

OK. So it's not about consistency with the other INREGs, its to do with them rarely being used for vectors?

I think you reasoning makes a lot of sense. Plus anyone using these nodes downstream and relying on it being Legal will likely have tests for the sext_inreg patterns they added, so should easily catch any differences.

If the hexagon changes are OK here, I'm happy.



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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:183
   setOperationAction(ISD::VSELECT,           VT, Expand);
-  setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
   if (VT.isInteger()) {
----------------
You can leave this line in. It's not bad to be explicit about this being expand.


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Comment at: llvm/test/CodeGen/Thumb2/mve-sext.ll:4
 
+define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32(<4 x i32> %m) {
+; CHECK-LABEL: sext_v4i32_v4i32:
----------------
Can you add equivalents for v8i16, v16i8 and maybe v2i64?

Or actually, I can do it later. I don't want to give you more work to do.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000