[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 229252.
steven.zhang added a comment.

Remove the NEON + MVE test, and add one test in mve-sext.ll, which will fail without this patch.

  LLVM ERROR: Cannot select: t13: v4i32 = sign_extend_inreg t3, ValueType:ch:v4i1
    t3: v4i32 = bitcast t2
      t2: v2f64,ch = CopyFromReg t0, Register:v2f64 %0
        t1: v2f64 = Register %0
  In function: sext_v4i32_v4i32

The reason is the same as Hexagon, Mips and other targets. That is, we are setting the default operation action for sext_inreg for vector type as legal.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000

Files:
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
  llvm/test/CodeGen/ARM/signext-inreg.ll
  llvm/test/CodeGen/Hexagon/signext-inreg.ll
  llvm/test/CodeGen/Thumb2/mve-sext.ll

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