[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

A few nits



================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:1
+//==- RISCVSchedRocket.td - Rocket Scheduling Definitions -*- tablegen -*-=//
+//
----------------
This should match the filename.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:9
+//
+// This file defines the itinerary class data for the ARM Cortex A53 processors.
+//
----------------
Hmmmm :)


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:1
+//==- RISCVSchedRocket.td - Rocket Scheduling Definitions -*- tablegen -*-=//
+//
----------------
This should match the filename.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:9
+//
+// This file defines the itinerary class data for the ARM Cortex A53 processors.
+//
----------------
Hmmmm :)


Repository:
  rL LLVM

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  https://reviews.llvm.org/D68685/new/

https://reviews.llvm.org/D68685