[PATCH] D68685: [RISCV] Scheduler description for Rocket Core
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 10 08:03:33 PDT 2019
luismarques added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:79
+
+// What is the correct latecny to model for fence instructions?
+def : WriteRes<WriteFence, [Rocket32UnitMem]>;
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typo
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rL LLVM
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https://reviews.llvm.org/D68685/new/
https://reviews.llvm.org/D68685
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