[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoM.td:35
-def REMU    : ALU_rr<0b0000001, 0b111, "remu">;
-} // Predicates = [HasStdExtM]
 
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Predicates are removed by accident?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68685/new/

https://reviews.llvm.org/D68685