[PATCH] D68121: [X86] Model MXCSR for all SSE instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Does this really not affect any tests? I would have thought some test would print MIR output that would show the implicit use that wasn't there before.



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Comment at: llvm/lib/Target/X86/X86InstrFormats.td:230
 class NOTRACK { bit hasNoTrackPrefix = 1; }
+class SIMD_EXP { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; }
 
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Is EXP an abbreviation for Exception? If so, I think EXC is probably a better abbreviation


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D68121/new/

https://reviews.llvm.org/D68121