[PATCH] D68121: [X86] Model MXCSR for all SSE instructions

[Pengfei Wang via Phabricator via llvm-commits]

pengfei created this revision.
pengfei added reviewers: craig.topper, RKSimon, andrew.w.kaylor, uweigand, kpn.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This patch adds MXCSR as a reserved physical register and models its use
by X86 SSE instructions. It also adds flag "mayRaiseFPException" for the
instructions that possibly can raise FP exception according to the
architecture definition.

Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled.  *Changes* of the MXCSR
due to exceptions are not modeled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D68121

Files:
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td

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