[PATCH] D67487: [CodeEmitter] Support instruction widths > 64 bits

[Artem Belevich via Phabricator via llvm-commits]

tra added inline comments.


================
Comment at: llvm/test/TableGen/BigEncoder.td:2
+// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
----------------
I'd add some details explaining what the test does and why.
Otherwise it's not clear what this test does and why without the full context of the patch.
Those `bits<65>` are not very noticeable on their own.


================
Comment at: llvm/test/TableGen/BigEncoder.td:59-69
+// CHECK-LABEL: case ::biz: {
+// CHECK: const APInt [[x:M[0-9]+]] = APInt::getBitsSet(65, 3, 7);
+// CHECK-NEXT: Value |= (op & [[x]]) << 9;
+// CHECK-NEXT: const APInt [[y:M[0-9]+]] = APInt::getBitsSet(65, 7, 11);
+// CHECK-NEXT: Value |= (op & [[y]]) << 1;
+
+// CHECK-LABEL: case ::foo: {
----------------
checks for results of `bar`/`baz` are missing. 


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67487/new/

https://reviews.llvm.org/D67487