[PATCH] D67487: [CodeEmitter] Support instruction widths > 64 bits

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL371929: [CodeEmitter] Improve testing for APInt encoding (authored by jamesm, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D67487?vs=219875&id=220242#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67487/new/

https://reviews.llvm.org/D67487

Files:
  llvm/trunk/test/TableGen/BigEncoder.td


Index: llvm/trunk/test/TableGen/BigEncoder.td
===================================================================
--- llvm/trunk/test/TableGen/BigEncoder.td
+++ llvm/trunk/test/TableGen/BigEncoder.td
@@ -45,17 +45,8 @@
     field bits<16> SoftFail = 0;
     }
 
-def baz : Instruction {
-    let InOperandList = (ins Myi32:$factor);
-    field bits<65> Inst;
-    bits<32> factor;
-    let Inst{7-0} = 0xDD;
-    let Inst{15-8} = factor{11-4}; // offset by 4 + custom decode
-    let AsmString = "baz  $factor";
-    field bits<16> SoftFail = 0;
-    }
-
 }
+
 // CHECK-LABEL: case ::biz: {
 // CHECK: const APInt [[x:M[0-9]+]] = APInt::getBitsSet(65, 3, 7);
 // CHECK-NEXT: Value |= (op & [[x]]) << 9;
@@ -67,3 +58,9 @@
 // CHECK-NEXT: op &= [[x]];
 // CHECK-NEXT: op <<= 8;
 // CHECK-NEXT: Value |= op;
+
+// CHECK-LABEL: case ::bar: {
+// CHECK: const APInt [[x:M[0-9]+]] = APInt::getBitsSet(65, 3, 11);
+// CHECK-NEXT: op &= [[x]];
+// CHECK-NEXT: op <<= 5;
+// CHECK-NEXT: Value |= op;


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