[PATCH] D67110: AMDGPU: Make VReg_1 size be 1

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked an inline comment as done.
arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:677
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
-  let Size = 32;
+  let Size = 1;
 }
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rampitec wrote:
> This is spill size. How does that work when spill size if 1?
VReg_1 should never be seen by a spill. This could also be rounded when spilling


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67110/new/

https://reviews.llvm.org/D67110