[PATCH] D67110: AMDGPU: Make VReg_1 size be 1

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: lib/Target/AMDGPU/SILowerI1Copies.cpp:497
+  unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
+  return Size == 1 || Size == 32;
+}
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SReg_1 is also 1 bit, but not necessarily 32 on spill.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:677
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
-  let Size = 32;
+  let Size = 1;
 }
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This is spill size. How does that work when spill size if 1?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67110/new/

https://reviews.llvm.org/D67110