[PATCH] D66882: [DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix updated this revision to Diff 217916.
deadalnix added a comment.

Tighten the checks before creating the node.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66882/new/

https://reviews.llvm.org/D66882

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/rotate-extract-vector.ll
  test/CodeGen/X86/rotate-extract.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D66882.217916.patch
Type: text/x-patch
Size: 4817 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190829/27f03b02/attachment.bin>