[PATCH] D66882: [DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Precommit tests pls.
Please add commutative test - `or` is commutative.



================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6026
 ///
+///   (or (add v v) (shrl v c)):
+///     expands (add v v) -> (shl v 1)
----------------
I suppose `add v v` implies that `c` can only be `bitwidth-1`


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https://reviews.llvm.org/D66882