[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill marked 3 inline comments as done.
lewis-revill added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:471
+bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
+    MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
+  return true;
----------------
luismarques wrote:
> AArch64 has more checks, some of which seem like could be relevant for us. Checking for section markings, link once, etc.
I've added the basic checks here, I will look into adding tests for this.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.ll:1
+; RUN: llc -march riscv32 < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -march riscv32 -enable-machine-outliner < %s \
----------------
paquette wrote:
> I recommend writing a .mir test for this instead of a .ll test. (e.g, use -stop-before=machine-outliner -simplify-mir)
> 
> That would make the test resilient against other code generation changes, and make it easier to test the instruction sequences you want to test.
I haven't used the tool in this way before, I've been trying to replicate the command used in the AArch64 run line, but I'm still getting 'error: expected top-level entity' when running the check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210