[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

Lewis Revill via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 22 02:43:03 PDT 2019


lewis-revill updated this revision to Diff 216571.
lewis-revill added a comment.

Rebased and addressed a couple of comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/machineoutliner.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D66210.216571.patch
Type: text/x-patch
Size: 9143 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190822/b9710a69/attachment.bin>


More information about the llvm-commits mailing list