[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/machineoutliner.ll:1
+; RUN: llc -march riscv32 < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -march riscv32 -enable-machine-outliner < %s \
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lewis-revill wrote:
> paquette wrote:
> > I recommend writing a .mir test for this instead of a .ll test. (e.g, use -stop-before=machine-outliner -simplify-mir)
> > 
> > That would make the test resilient against other code generation changes, and make it easier to test the instruction sequences you want to test.
> I haven't used the tool in this way before, I've been trying to replicate the command used in the AArch64 run line, but I'm still getting 'error: expected top-level entity' when running the check.
"expected top-level entity" comes from the IR parser, so your testcase probably isn't getting treated as MIR at all.

MIR testcases have to end with a ".mir" extension (or you can use "-x mir").


Repository:
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  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210