[PATCH] D66132: [CodeGen] Add `shouldDoPartialRedundancyElimination()` to `TargetInstrInfo` (PRR42405)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev updated this revision to Diff 215040.
anton-afanasyev marked 2 inline comments as done.
anton-afanasyev added a comment.

Rename


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66132/new/

https://reviews.llvm.org/D66132

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MachineCSE.cpp


Index: llvm/lib/CodeGen/MachineCSE.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCSE.cpp
+++ llvm/lib/CodeGen/MachineCSE.cpp
@@ -887,8 +887,10 @@
   DT = &getAnalysis<MachineDominatorTree>();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   LookAheadLimit = TII->getMachineCSELookAheadLimit();
-  bool ChangedPRE, ChangedCSE;
-  ChangedPRE = PerformSimplePRE(DT);
+  bool ChangedPRE = false, ChangedCSE;
+  if (!TII->shouldDoPartialRedundancyElimination()) {
+    ChangedPRE = PerformSimplePRE(DT);
+  }
   ChangedCSE = PerformCSE(DT->getRootNode());
   return ChangedPRE || ChangedCSE;
 }
Index: llvm/include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1022,6 +1022,11 @@
   /// even if it has glue.
   virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
 
+  /// Return true if speculative execution of target instructions is forbidden.
+  /// This prevents MIR code from SimplePRE optimization leading to possible
+  /// speculative execution of instructions.
+  virtual bool shouldDoPartialRedundancyElimination() const { return false; }
+
 protected:
   /// Target-dependent implementation for foldMemoryOperand.
   /// Target-independent code in foldMemoryOperand will


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