[PATCH] D65683: MVT: Add v3i16/v3f16 vectors

Fri Aug 2 20:45:44 PDT 2019

arsenm marked 2 inline comments as done.
arsenm added inline comments.

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Comment at: test/CodeGen/X86/promote-vec3.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
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craig.topper wrote:
> Can you explain why the X86 tests changed?
That it’s now an MVT places it into the legalization action table, and now defaults to widen as per getPreferredVectorAction. As an EVT, it would default to Expand. computeRegisterProperties scans over all MVT values, so the existence of a new MVT can change the legalization default regardless of the legal register types

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Comment at: utils/TableGen/IntrinsicEmitter.cpp:224
+  IIT_VEC_ELEMENT = 42,
+  IIT_V48  = 43
 };
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craig.topper wrote:
> Is this needed for this patch or a future patch that adds an intrinsic?
I hit this I think due to a bug in updating the ValueTypes.td enum values and can probably be dropped.  The only intrinsics that would use this use a mangled parameter

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65683/new/

https://reviews.llvm.org/D65683