[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

[Piotr Sobczak via Phabricator via llvm-commits]

piotr added a comment.

This opt opportunity presents itself after the register coalescer, where inline constants are moved to the same registers (attaching IR example testcase imminently). MachineCSE is run too early to spot this and the last occurence of si-shrink-instructions is run at the right time. I think, for similar reasons some other peepholes were also placed in this pass, even though they are not about 32-bit encoding.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63709/new/

https://reviews.llvm.org/D63709