[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

Mon Jun 24 08:42:12 PDT 2019

rampitec requested changes to this revision.
rampitec added a comment.
This revision now requires changes to proceed.

Patch does not take control flow divergence into account.

================
Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:682
+        if (Src.isImm() &&
+            TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) {
+
----------------
Even is block has only one predecessor that does not mean this is the reaching def of the physreg. The predecessor may (and likely will) have a different exec mask. It might work with sclaral, but not with vector moves.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63709/new/

https://reviews.llvm.org/D63709