[PATCH] D63709: [AMDGPU] Add peephole to optimize MOV

Mon Jun 24 08:59:12 PDT 2019

piotr marked an inline comment as done.
piotr added inline comments.

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Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:682
+        if (Src.isImm() &&
+            TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) {
+
----------------
rampitec wrote:
> Even is block has only one predecessor that does not mean this is the reaching def of the physreg. The predecessor may (and likely will) have a different exec mask. It might work with sclaral, but not with vector moves.
Perhaps I misunderstood your comment, but if the block has only one predecessor then it is executed for a subset of threads that already executed the predecessor, so for that subset we're sure that the previous mov happened?

Repository:
  rL LLVM

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  https://reviews.llvm.org/D63709/new/

https://reviews.llvm.org/D63709