[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/MC/AMDGPU/offsetbug.s:1-7
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s --check-prefix=GFX10
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx1010 - | FileCheck %s --check-prefix=BIN
+	s_getpc_b64 s[0:1]
+	s_cbranch_vccnz BB0_2
+// GFX10: s_cbranch_vccnz BB0_2           ; encoding: [A,A,0x87,0xbf]
+// GFX10-NEXT: ;   fixup A - offset: 0, value: BB0_2, kind: fixup_si_sopp_br
+// BIN: s_cbranch_vccnz BB0_2 // 000000000004: BF870061
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Can you split the test into separate files? I think there should be one function that needs 1 relaxation, another where the relaxation of one triggers the relaxation of the other, and another that triggers this twice


Repository:
  rL LLVM

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  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494