[PATCH] D62598: [AArch64][ELF][llvm-objdump] Add support for PLT decoding with BTI instructions present

[Peter Smith via Phabricator via llvm-commits]

peter.smith created this revision.
peter.smith added reviewers: jhenderson, grimar, jakehehrlich, LukeCheeseman.
Herald added subscribers: rupprecht, kristof.beyls, javed.absar.

Arm Architecture v8.5a introduces Branch Target Identification (BTI). When enabled all indirect branches must target a bti instruction of the appropriate form. As PLT sequences may sometimes be the target of an indirect branch and PLT[0] always is, a static linker may need to generate PLT sequences that contain "bti c" as the first instruction. In effect:

  bti     c
  adrp    x16, page offset to .got.plt
  ...

Instead of:

  adrp    x16, page offset to .got.plt
  ...

At present the PLT decoding assumes the adrp will always be the first instruction. This patch adds support for a single optional "bti c" to prefix the adrp. A test binary has been uploaded with such a PLT sequence. The existing code already supports the PAC PLT sequence that adds an AUTIA1716 before the BR X17. A forthcoming LLD patch will make heavy use of the PLT decoding code.

The encoding for BTI c can be found in https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf


https://reviews.llvm.org/D62598

Files:
  lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  test/tools/llvm-objdump/AArch64/Inputs/bti-pac-plt.elf-aarch64
  test/tools/llvm-objdump/AArch64/plt.test


Index: test/tools/llvm-objdump/AArch64/plt.test
===================================================================
--- test/tools/llvm-objdump/AArch64/plt.test
+++ test/tools/llvm-objdump/AArch64/plt.test
@@ -2,4 +2,21 @@
 
 # CHECK: Disassembly of section .plt:
 # CHECK: __cfi_slowpath at plt:
+# CHECK-NEXT: adrp      x16, {{.*}}
 # CHECK: bl {{.*}} <__cfi_slowpath at plt>
+
+// RUN: llvm-objdump -d -mattr=+bti %p/Inputs/bti-pac-plt.elf-aarch64 | \
+// RUN:   FileCheck --check-prefix=CHECK-BTI %s
+# CHECK-BTI: bl {{.*}} <f1 at plt>
+# CHECK-BTI: bl {{.*}} <f2 at plt>
+# CHECK-BTI: bl {{.*}} <f3 at plt>
+# CHECK-BTI: Disassembly of section .plt:
+# CHECK-BTI: f1 at plt:
+# CHECK-BTI-NEXT: bti   c
+# CHECK-BTI-NEXT: adrp  x16, {{.*}}
+# CHECK-BTI: f2 at plt:
+# CHECK-BTI-NEXT: bti   c
+# CHECK-BTI-NEXT: adrp  x16, {{.*}}
+# CHECK-BTI: f3 at plt:
+# CHECK-BTI-NEXT: bti   c
+# CHECK-BTI-NEXT: adrp  x16, {{.*}}
Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -166,12 +166,20 @@
     for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
          Byte += 4) {
       uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
+      uint64_t Off = 0;
+      // Check for optional bti c that prefixes adrp in BTI enabled entries
+      if ((Insn & 0xd503245f) == 0xd503245f) {
+         Off = 4;
+         Insn = support::endian::read32le(PltContents.data() + Byte + Off);
+      }
       // Check for adrp.
       if ((Insn & 0x9f000000) != 0x90000000)
         continue;
+      Off += 4;
       uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
             (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
-      uint32_t Insn2 = support::endian::read32le(PltContents.data() + Byte + 4);
+      uint32_t Insn2 =
+          support::endian::read32le(PltContents.data() + Byte + Off);
       // Check for: ldr Xt, [Xn, #pimm].
       if (Insn2 >> 22 == 0x3e5) {
         Imm += ((Insn2 >> 10) & 0xfff) << 3;


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