[PATCH] D62597: [mips] Extend range of register indexes accepted by cfcmsa/ctcmsa
Simon Atanasyan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 1 06:54:08 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rG25694e008444: [mips] Extend range of register indexes accepted by cfcmsa/ctcmsa (authored by atanasyan).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62597/new/
https://reviews.llvm.org/D62597
Files:
llvm/lib/Target/Mips/MipsRegisterInfo.td
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
Index: llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
===================================================================
--- llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
+++ llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
@@ -84,6 +84,15 @@
; CHECK: cfcmsa $[[R1:[0-9]+]], $7
; CHECK: .size msa_unmap_cfcmsa_test
;
+define i32 @msa_invalid_reg_cfcmsa_test() nounwind {
+entry:
+ %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
+ ret i32 %0
+}
+
+; CHECK-LABEL: msa_invalid_reg_cfcmsa_test:
+; CHECK: cfcmsa ${{[0-9]+}}, $8
+;
define void @msa_ir_ctcmsa_test() nounwind {
entry:
tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
@@ -164,5 +173,14 @@
; CHECK: ctcmsa $7
; CHECK: .size msa_unmap_ctcmsa_test
;
+define void @msa_invalid_reg_ctcmsa_test() nounwind {
+entry:
+ tail call void @llvm.mips.ctcmsa(i32 8, i32 1)
+ ret void
+}
+
+; CHECK: msa_invalid_reg_ctcmsa_test:
+; CHECK: ctcmsa $8
+;
declare i32 @llvm.mips.cfcmsa(i32) nounwind
declare void @llvm.mips.ctcmsa(i32, i32) nounwind
Index: llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -75,18 +75,8 @@
}
unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
- switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
- default:
- llvm_unreachable("Could not map int to register");
- case 0: return Mips::MSAIR;
- case 1: return Mips::MSACSR;
- case 2: return Mips::MSAAccess;
- case 3: return Mips::MSASave;
- case 4: return Mips::MSAModify;
- case 5: return Mips::MSARequest;
- case 6: return Mips::MSAMap;
- case 7: return Mips::MSAUnmap;
- }
+ uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
+ return Mips::MSACtrlRegClass.getRegister(RegNum);
}
bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
Index: llvm/lib/Target/Mips/MipsRegisterInfo.td
===================================================================
--- llvm/lib/Target/Mips/MipsRegisterInfo.td
+++ llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -258,6 +258,11 @@
def MSARequest : MipsReg<5, "5">;
def MSAMap : MipsReg<6, "6">;
def MSAUnmap : MipsReg<7, "7">;
+ // MSA-ASE fake control registers.
+ // These registers do not exist, but instructions like `cfcmsa`
+ // and `ctcmsa` allows to specify them.
+ foreach I = 8-31 in
+ def MSA#I : MipsReg<#I, ""#I>;
// Octeon multiplier and product registers
def MPL0 : MipsReg<0, "mpl0">;
@@ -438,7 +443,8 @@
(decimate (sequence "W%u", 0, 31), 2)>;
def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
- MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
+ MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap,
+ (sequence "MSA%u", 8, 31))>, Unallocatable;
// Hi/Lo Registers
def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
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