[PATCH] D62360: [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

pre-commit the zero idiom tests?



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Comment at: llvm/lib/Target/X86/X86SchedBroadwell.td:1606
+// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
+// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
+// renaming".
----------------
Haswell and Broadwell?


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Comment at: llvm/lib/Target/X86/X86SchedHaswell.td:1859
+// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
+// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
+// renaming".
----------------
Haswell and Broadwell?


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Comment at: llvm/lib/Target/X86/X86SchedSkylakeClient.td:1747
+// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
+// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
+// renaming".
----------------
Skylake?


================
Comment at: llvm/lib/Target/X86/X86SchedSkylakeServer.td:2463
+// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
+// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
+// renaming".
----------------
Skylake?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62360/new/

https://reviews.llvm.org/D62360