[PATCH] D62360: [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models. Add 256-bit fp xor to sandybridge zero idioms

[Clement Courbet via Phabricator via llvm-commits]

courbet accepted this revision.
courbet added a comment.
This revision is now accepted and ready to land.

Thanks.



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Comment at: llvm/lib/Target/X86/X86SchedSandyBridge.td:1163
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
-    SchedVar<NoSchedPred,                          [SBWriteResGroup30]>
+    SchedVar<NoSchedPred,                          [SBWritePCMPGTQ]>
 ]>;
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craig.topper wrote:
> I didn't like the reference to ResGroup30 since someone could easily rearrange numbers and not know this was dependent. So I copied the class and gave it a better name.
Makes sense.


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https://reviews.llvm.org/D62360