[PATCH] D62028: [DebugInfo][AArch64] Recognise target specific instruction as mov instr

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:5512
+  // AArch64::ORRWrs and AArch64::ORRXrs with zero immediate
+  // used as an alias for mov instruction.
+  if ( MI.getOpcode() == AArch64::ORRWrs || MI.getOpcode() == AArch64::ORRXrs ) {
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I don't think we'll produce an ORRXrs until after it's relevant here, but I guess it's safe enough.

You need to check that the instruction is actually a "mov"; it looks like you're correctly checking that the shift amount is zero, but you aren't checking that the other register is wzr/xzr.


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Comment at: llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.ll:24
+;   for(int i = 1; i < argc; ++i) {
+;     printf("Argument %d: %s\n", i, argv[i]);
+;   }
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Can you make an MIR testcase using -run-pass instead of running the complete llc pipeline?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62028/new/

https://reviews.llvm.org/D62028