[PATCH] D60459: SILoadStoreOptimizer pass mischedules s_add,s_addc with interfering s_lshl

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/scc-has-add.mir:10-12
+  source_filename = "<stdin>"
+  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
+
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You can drop the block names, and IR references in the MMOs to drop the IR section


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Comment at: test/CodeGen/AMDGPU/scc-has-add.mir:113-115
+    ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr101
+    %5:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @__ockl_get_local_size + 4, target-flags(amdgpu-gotprel32-hi) @__ockl_get_local_size + 4, implicit-def dead $scc
+    %6:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed %5, 0, 0 :: (dereferenceable invariant load 8 from got, addrspace 4)
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You can strip out a lot of instructions too. Usually I just create a smaller, totally artificial test case from scratch


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60459/new/

https://reviews.llvm.org/D60459