[PATCH] D60459: SILoadStoreOptimizer pass mischedules s_add,s_addc with interfering s_lshl

Fri Apr 12 14:38:28 PDT 2019

ronlieb marked 2 inline comments as done.
ronlieb added inline comments.

================
Comment at: test/CodeGen/AMDGPU/scc-has-add.mir:10-12
+  source_filename = "<stdin>"
+  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
+
----------------
arsenm wrote:
> You can drop the block names, and IR references in the MMOs to drop the IR section
The SILoadStoreOptimizer pass depends on Alias analysis on memory references as part of its decision to collect a group of instructions. So when i attempt to removes this information from the MIR, the test does not reproduce the issue. Similiarly, trying to remove the IR section also introduces issues with reproducing the issue, as their are PC relative definitions needed in the MIR test. So i think i need to keep the MIR test as is with a bit of cleanup. Also, since the scc-has-add.mir .test closely replicates the scc-add-lshl-addc.ll test, i plan to keep the .ll test, dump the scc-has-add.mir test, and keep the scc-missing-add,mir test.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60459/new/

https://reviews.llvm.org/D60459