[PATCH] D60546: [X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 194637.
craig.topper added a comment.

Support seq_cst store by inserting an mfence after the store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60546/new/

https://reviews.llvm.org/D60546

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/test/CodeGen/X86/atomic-fp.ll
  llvm/test/CodeGen/X86/atomic-load-store-wide.ll
  llvm/test/CodeGen/X86/atomic-non-integer.ll
  llvm/test/CodeGen/X86/atomic6432.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D60546.194637.patch
Type: text/x-patch
Size: 31253 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190411/b40d836e/attachment.bin>