[PATCH] D60546: [X86] Use MOVQ for i64 non-seq_cst atomic_stores when SSE2 is enabled

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked 2 inline comments as done.
craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/X86/atomic-fp.ll:152
 ; X86-SSE2-NEXT:    addsd 12(%ebp), %xmm0
 ; X86-SSE2-NEXT:    movsd %xmm0, (%esp)
+; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
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There is an extra stack temporary here due to type legalization of the bitcast from f64 to i64 being legalized as a stack store f64 and then two i32 loads. DAG combine was able to merge the loads probably using merge elts from consecutive loads to create a VZEXT_LOAD.


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Comment at: llvm/test/CodeGen/X86/atomic6432.ll:841
+; X32-NEXT:    movd %ecx, %xmm0
+; X32-NEXT:    pinsrd $1, %eax, %xmm0
+; X32-NEXT:    movq %xmm0, sc64
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Not sure why we didn't merge consecutive loads here.


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  https://reviews.llvm.org/D60546/new/

https://reviews.llvm.org/D60546