[PATCH] D60137: Describe stack-id as an enum

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 4 08:49:08 PDT 2019 

sdesmalen updated this revision to Diff 193730.
sdesmalen added a comment.

- Renamed `sgpr_spill` -> `sgpr-spill`.
- Renamed `TargetStackID::SGPR_Spill` -> `TargetStackID::SGPRSpill`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60137/new/

https://reviews.llvm.org/D60137

Files:
  include/llvm/CodeGen/MIRYamlMapping.h
  include/llvm/CodeGen/TargetFrameLowering.h
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineFrameInfo.cpp
  lib/CodeGen/PrologEpilogInserter.cpp
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIFrameLowering.h
  lib/Target/AMDGPU/SIInstrInfo.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
  test/CodeGen/AArch64/GlobalISel/call-translator.ll
  test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
  test/CodeGen/AArch64/GlobalISel/legalize-load-vector.mir
  test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
  test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
  test/CodeGen/AArch64/branch-target-enforcment.mir
  test/CodeGen/AArch64/cfi_restore.mir
  test/CodeGen/AArch64/reverse-csr-restore-seq.mir
  test/CodeGen/AArch64/spill-stack-realignment.mir
  test/CodeGen/AArch64/stack-id-pei-alloc.mir
  test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
  test/CodeGen/AArch64/wineh-frame5.mir
  test/CodeGen/AArch64/wineh-frame6.mir
  test/CodeGen/AArch64/wineh-frame7.mir
  test/CodeGen/AArch64/wineh-frame8.mir
  test/CodeGen/AArch64/wineh1.mir
  test/CodeGen/AArch64/wineh2.mir
  test/CodeGen/AArch64/wineh3.mir
  test/CodeGen/AArch64/wineh4.mir
  test/CodeGen/AArch64/wineh5.mir
  test/CodeGen/AArch64/wineh6.mir
  test/CodeGen/AArch64/wineh7.mir
  test/CodeGen/AArch64/wineh8.mir
  test/CodeGen/AArch64/wineh_shrinkwrap.mir
  test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
  test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
  test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
  test/CodeGen/ARM/constant-island-movwt.mir
  test/CodeGen/ARM/fp16-litpool-arm.mir
  test/CodeGen/ARM/fp16-litpool-thumb.mir
  test/CodeGen/ARM/fp16-litpool2-arm.mir
  test/CodeGen/ARM/fp16-litpool3-arm.mir
  test/CodeGen/ARM/register-scavenger-exceptions.mir
  test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
  test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
  test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
  test/CodeGen/MIR/AMDGPU/stack-id.mir
  test/CodeGen/MIR/X86/branch-folder-with-label.mir
  test/CodeGen/MIR/X86/diexpr-win32.mir
  test/CodeGen/MIR/X86/fixed-stack-di.mir
  test/CodeGen/MIR/X86/fixed-stack-objects.mir
  test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
  test/CodeGen/MIR/X86/stack-objects.mir
  test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
  test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
  test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
  test/CodeGen/Mips/GlobalISel/legalizer/add.mir
  test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
  test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
  test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir
  test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
  test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
  test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
  test/CodeGen/Mips/micromips-eva.mir
  test/CodeGen/Mips/micromips-short-delay-slot.mir
  test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
  test/CodeGen/Mips/micromips-sizereduction/micromips-movep.mir
  test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
  test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
  test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
  test/CodeGen/PowerPC/setcr_bc.mir
  test/CodeGen/PowerPC/setcr_bc2.mir
  test/CodeGen/PowerPC/setcr_bc3.mir
  test/CodeGen/SystemZ/debuginstr-02.mir
  test/CodeGen/SystemZ/subregliveness-06.mir
  test/CodeGen/Thumb/PR36658.mir
  test/CodeGen/Thumb2/high-reg-spill.mir
  test/CodeGen/Thumb2/peephole-cmp.mir
  test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir
  test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir
  test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir
  test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
  test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
  test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir
  test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
  test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
  test/CodeGen/X86/GlobalISel/x86-select-srem.mir
  test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
  test/CodeGen/X86/GlobalISel/x86-select-urem.mir
  test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir
  test/CodeGen/X86/PR37310.mir
  test/CodeGen/X86/avoid-sfb-offset.mir
  test/CodeGen/X86/movtopush.mir
  test/CodeGen/X86/pr30821.mir
  test/CodeGen/X86/regalloc-copy-hints.mir
  test/CodeGen/X86/shrink_wrap_dbg_value.mir
  test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
  test/DebugInfo/AArch64/asan-stack-vars.mir
  test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir
  test/DebugInfo/ARM/cfi-eof-prologue.mir
  test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
  test/DebugInfo/MIR/Mips/last-inst-bundled.mir
  test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
  test/DebugInfo/MIR/X86/debug-loc-0.mir
  test/DebugInfo/MIR/X86/kill-after-spill.mir
  test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
  test/DebugInfo/MIR/X86/live-debug-values-restore.mir
  test/DebugInfo/X86/debug-loc-asan.mir
  test/DebugInfo/X86/debug-loc-offset.mir
  test/DebugInfo/X86/dw_op_minus.mir
  test/DebugInfo/X86/live-debug-vars-dse.mir
  test/DebugInfo/X86/pr19307.mir
  test/DebugInfo/X86/prolog-params.mir

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