[PATCH] D60261: [Option A] Change semantics of fadd/fmul vector reductions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
Herald added a subscriber: javed.absar.

NOTE: This is currently only a proposal as referenced in an RFC on llvm-dev mailing list.

This patch changes how LLVM handles the accumulator/start value
in the reduction, by never ignoring it regardless of the presence of
fast-math flags on callsites. This change introduces the following
new intrinsics to replace the existing ones:

  llvm.experimental.vector.reduce.fadd -> llvm.experimental.vector.reduce.v2.fadd
  llvm.experimental.vector.reduce.fmul -> llvm.experimental.vector.reduce.v2.fmul

and adds functionality to auto-upgrade existing LLVM IR and bitcode.


https://reviews.llvm.org/D60261

Files:
  docs/LangRef.rst
  include/llvm/CodeGen/BasicTTIImpl.h
  include/llvm/IR/Intrinsics.td
  lib/CodeGen/ExpandReductions.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/IR/AutoUpgrade.cpp
  lib/IR/IRBuilder.cpp
  lib/Transforms/Utils/LoopUtils.cpp
  test/Assembler/invalid-vecreduce.ll
  test/Bitcode/upgrade-vecreduce-intrinsics.ll
  test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc
  test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
  test/CodeGen/AArch64/vecreduce-fadd.ll
  test/CodeGen/Generic/expand-experimental-reductions.ll
  test/CodeGen/X86/haddsub.ll
  test/CodeGen/X86/vector-reduce-fadd-fast.ll
  test/CodeGen/X86/vector-reduce-fadd.ll
  test/CodeGen/X86/vector-reduce-fmul-fast.ll
  test/CodeGen/X86/vector-reduce-fmul.ll

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