[PATCH] D60262: [Option B] Create explicit ordered/unordered reduction intrinsics for fadd/fmul.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
Herald added a subscriber: javed.absar.

NOTE: This is currently only a proposal as referenced in an RFC on llvm-dev mailing list.

This patch creates explicit ordered and unordered reduction intrinsics for
fadd and fmul and adds functionality to auto-upgrade existing LLVM IR
and bitcode to use the new intrinsics.

      
  llvm.experimental.vector.reduce.fadd -> llvm.experimental.vector.reduce.ordered.fadd

fast llvm.experimental.vector.reduce.fadd -> llvm.experimental.vector.reduce.unordered.fadd

      
  llvm.experimental.vector.reduce.fmul -> llvm.experimental.vector.reduce.ordered.fmul

fast llvm.experimental.vector.reduce.fmul -> llvm.experimental.vector.reduce.unordered.fmul


https://reviews.llvm.org/D60262

Files:
  docs/LangRef.rst
  include/llvm/CodeGen/BasicTTIImpl.h
  include/llvm/IR/IRBuilder.h
  include/llvm/IR/Intrinsics.td
  lib/CodeGen/ExpandReductions.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/IR/AutoUpgrade.cpp
  lib/IR/IRBuilder.cpp
  lib/Transforms/Utils/LoopUtils.cpp
  test/Assembler/invalid-vecreduce.ll
  test/Bitcode/upgrade-vecreduce-intrinsics.ll
  test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc
  test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
  test/CodeGen/AArch64/vecreduce-fadd.ll
  test/CodeGen/Generic/expand-experimental-reductions.ll
  test/CodeGen/X86/haddsub.ll
  test/CodeGen/X86/vector-reduce-fadd-fast.ll
  test/CodeGen/X86/vector-reduce-fadd.ll
  test/CodeGen/X86/vector-reduce-fmul-fast.ll
  test/CodeGen/X86/vector-reduce-fmul.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D60262.193693.patch
Type: text/x-patch
Size: 84392 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190404/21074480/attachment-0001.bin>