[PATCH] D58899: [CodeGen] Prepare for introduction of v3 and v5 MVTs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

The ARM patch at least should be split into a separate patch



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Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:1034
         MemVT = MemVT.getPow2VectorType(State.getContext());
-      }
+      else
+        assert(!MemVT.isExtended() &&
----------------
Braces


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Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:1036
+        assert(!MemVT.isExtended() &&
+               (!MemVT.isVector() || MemVT.isPow2VectorType()));
 
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Should also make sure to add some 5x vector argument tests to the kernarg tests since you are adding those


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Comment at: lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp:343
   EVT OrigTy = TLI->getValueType(DL, Ty);
-  if (!OrigTy.isSimple()) {
+  if (!OrigTy.isSimple() || (OrigTy.isVector() && !OrigTy.isPow2VectorType())) {
     return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
----------------
This could use a test in test/Analysis/CostModel/AMDGPU


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Comment at: lib/Target/ARM/ARMISelLowering.cpp:12153
   unsigned NumLanes = Op.getValueType().getVectorNumElements();
-  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
+  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4 || NumLanes == 3) {
     // These instructions only exist converting from f32 to i32. We can handle
----------------
Combine the last 2 checks into NumLanes >= 3


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:12211
   unsigned NumLanes = Op.getValueType().getVectorNumElements();
-  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
+  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4 || NumLanes == 3) {
     // These instructions only exist converting from i32 to f32. We can handle
----------------
Ditto


Repository:
  rL LLVM

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  https://reviews.llvm.org/D58899/new/

https://reviews.llvm.org/D58899